1. Field of the Invention
The present invention relates to a semiconductor device in which a metal-oxide-semiconductor field-effect transistor is formed in a silicon-on-sapphire substrate with a comparatively thin silicon layer.
2. Description of the Related Art
Forming semiconductor devices in silicon-on-sapphire (SOS) substrates with a comparatively thick layer of silicon, typically a layer about 0.3 micrometer (0.3 μm) thick, is an established art. To form a lightly doped drain (LDD) layer in a metal-oxide-semiconductor field-effect transistor (MOSFET) in such a substrate, for example, for an n-channel MOSFET, it is known to implant ions of phosphorus, which is an n-type impurity, into the body area of the MOSFET with a dose of 3×1013 ions/cm2 and an energy of thirty kilo-electron volts (30 keV), forming an LDD layer with a thickness of about one-tenth of a micrometer (0.1 μm), as described in Japanese Patent Application Publication No. 2003-69033 (paragraphs 0024-0025 and FIG. 1).
Recently, however, SOS substrates with comparatively thin silicon layers, 0.1 μm thick or less, have come into use. These substrates have the advantage of enabling MOSFETs to operate in a fully depleted mode, but if the conventional technology described above is used, the resulting LDD layer, which is itself about 0.1 μm thick, may extend to the silicon-sapphire interface, causing a problem of increased leakage current in the off-state, when the gate-source voltage is zero volts (Vgs=0 V). This problem is particularly serious in short-channel MOSFETs with a gate length of 1 μm or less. Use of thin-silicon SOS semiconductor devices with transistors of this type in battery-powered apparatus results in reduced battery life due, for example, to increased current flow in the standby state.
For reference, FIG. 1 shows an n-channel MOSFET 101, also referred to below as an nMOS device, having an LDD layer that reaches the silicon-sapphire interface. The nMOS device 101 is formed on an SOS substrate 4 comprising a sapphire substrate 2 and a silicon layer 3 at most 0.1 μm thick, which meet at an interface 5 indicated by a bold line. The nMOS device 101 includes: a source 6 and a drain 7 that are formed as n-type diffusions; a body region 8 formed as a p-type diffusion in the area between the source 6 and drain 7, where a channel forms when the device is in the on-state; a gate electrode 10 facing the body region 8 and insulated therefrom by a gate oxide film 9 such as a silicon oxide (SiO2) film; side walls 11 formed as silicon oxide films or other dielectric films on both sides of the gate electrode 10; and lightly doped n-type diffusion layers referred to as LDD layers 113, 114 formed in the body region beneath the gate electrode 10 on both the source side and the drain side, adjoining one end of the source 6 and one end of the drain 7, having a lower n-type impurity concentration than the source 6 and drain 7.
The inventor has investigated the cause of current leakage in this type of nMOS device 101, having a source side LDD 113 and a drain side LDD 114 that reach the interface 5, by using a device simulation program. FIG. 2 shows a simulation result indicating drain current characteristics of an nMOS device with a short channel; FIG. 3 shows a simulation result indicating the electron density distribution in this nMOS device when current leakage occurs; FIG. 4 shows a simulation result indicating ideal characteristics of an nMOS device with a short channel.
These simulation results were calculated for a short-channel nMOS device 101 formed on an SOS substrate 4 comprising a silicon layer 3 0.1 μm thick formed on a sapphire substrate 2, having a gate length of 0.25 μm. As shown in FIG. 2, the drain current per unit width (1 μm) of the gate 10 is 10−8 A/μm when the drain-source voltage Vds is 2.5 V and the gate-source voltage Vgs is 0 V (the off-state) This result shows a current leakage significantly higher than in the ideal off-state (drain current 10−10 A/μm).
FIG. 3 shows the electron density distribution in the device during this high leakage current flow, showing contours of electron density increasing by factors of ten from E=1014/cm3 to E=1020/cm3. The electron density contours equal to and less than E=1017/cm3 fold back to form an inversion layer in the body region 8 on the interface 5 between the silicon layer 3 and the sapphire substrate 2, in the area circled with the dashed line, forming an undesired back channel.
This simulation result indicates that current leakage in the off-state is caused by a back channel formed when a positive drain-source voltage is applied while the gate-source voltage is zero. This back channel differs from the channel (front channel) formed on the gate side of the body region 8 when a positive voltage is applied to the gate 10.